Principal Datacenter GPU Lead Power Constrained Performance Architect
About The Position
AMD’s Datacenter Performance Group is seeking a senior Power & Performance Architect for driving the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve owning the Perf@Power attainment of a leading generation of our Instinct accelerators, providing cross-functional leadership for a virtual team that drives all aspects of Perf@Power attainment, including pre-Si modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development. Being passionate about performance and power efficiency, influence without authority and excellent communication skills are key ingredients for success in this role.
Requirements
- Background in Computer Architecture, Processor/Accelerator development
- Experience in Power/Performance projections, modeling and optimization at SoC or System level
- Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..)
- Familiarity with post-silicon power/performance debug, model correlation
- Fluency in communicating with various engineering teams, business leads and executive management
Nice To Haves
- Knowledge of DL/ML/LLM/MoE workloads will be a bonus
Responsibilities
- Own power-constrained performance modeling, projections, implementation target setting and attainment tracking from Concept-exit (pre-si) to Product launch (post-si) for AMD Instinct AI/ML/HPC accelerators
- Work with business unit and product architecture to define product configurations, capabilities and P&P targets
- Cross functionally lead P&P attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, Post-si validation
- Roll-up Power/Performance readouts, present in executive forums, motivate cross-functional teams on power efficiency improvements
- Mentor junior engineers and develop skillsets and methodologies in the team for important PPA domains like Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade-offs and attainment, Silicon Power/Performance debug, Post Si calibration of models, Work-load power analysis
Benefits
- AMD benefits at a glance
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What This Job Offers
Job Type
Full-time
Career Level
Senior
