Hardware System Architecture Fellow - AI & Data Center Networking

Advanced Micro Devices, Inc•Santa Clara, CA

15h•Onsite

About The Position

The Hardware System Architecture Fellow – AI & Data Center Networking is the highest‑impact individual contributor responsible for defining and driving end‑to‑end hardware system architecture for AMD’s next‑generation AI and data center networking platforms. This role provides system‑level technical leadership, spanning architecture definition, cross‑domain trade‑offs, and resolution of the most complex hardware challenges across AI‑NICs, DPUs, switches, and rack‑scale networking solutions. The Fellow operates with enterprise‑scale technical authority, shaping multi‑generation system architectures and influencing execution across ASIC, packaging, board, optics, power, thermal, mechanical, firmware, and manufacturing domains, without direct people management responsibility. The ideal candidate is a recognized technical leader with deep system expertise, strong architectural judgment, and the ability to influence across organizations through credibility, clarity, and technical depth.

Requirements

Deep expertise in system‑level hardware architecture for networking, AI infrastructure, or data center platforms.
Proven track record of architecting and delivering complex hardware systems across multiple product generations.
Broad understanding of board design, power delivery, signal integrity, system validation, and high‑speed bring‑up.
Demonstrated ability to solve ambiguous, cross‑domain problems with significant technical and business impact.
Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Nice To Haves

Experience with AI scale‑out networking systems, including AI‑NICs, DPUs, or high‑bandwidth switching platforms.
Familiarity with advanced interconnect and packaging technologies and their system‑level implications.
Demonstrated enterprise‑level technical influence (e.g., architecture ownership, critical platform delivery, or Fellow trajectory).
Recognized industry or academic thought leadership, with publications, patents, or standards contributions.
PhD preferred

Responsibilities

Define system‑level architecture for AI scale‑out and scale‑up networking platforms, translating product and business requirements into robust, scalable hardware solutions.
Drive architectural decisions across chip‑to‑system boundaries, including interconnect topology, board and system partitioning, power delivery strategy, signal integrity constraints, and platform extensibility.
Lead early‑phase system feasibility analysis, proactively identifying risks, trade‑offs, and technology inflection points.
Serve as the primary technical authority for system‑level challenges spanning ASIC, packaging, board design, optics, power, thermal, and mechanical integration.
Resolve the most complex bring‑up, validation, and field issues, synthesizing cross‑domain data to drive root‑cause closure and architectural improvements.
Ensure architectural intent is preserved through design, validation, and production ramp.
Establish and evolve system architecture best practices, review frameworks, and decision‑making methodologies across NTSG.
Define standardized architecture review and system validation flows to improve predictability, reuse, and overall execution quality.
Champion a disciplined system‑level engineering mindset across hardware development organizations.
Influence senior engineers, architects, and leaders across organizations through technical depth and credibility, rather than authority.
Mentor Principal and PMTS engineers on system architecture, trade‑off analysis, and Fellow‑level technical growth.
Represent NTSG in cross‑organization architecture reviews and Fellow‑level technical forums.
Shape multi‑generation system and platform roadmaps aligned with AMD’s AI networking strategy.
Anticipate and lead architectural transitions in bandwidth scaling, optical adoption, power density, and rack‑level integration.
Guide organizations through major architectural shifts while minimizing execution risk.