CAD/EDA Manager

Neurophos • Austin, TX

1d • $220,000 - $255,000 • Onsite

About The Position

Neurophos is a startup focused on addressing the energy and power limitations of traditional silicon chips for data centers and AI compute. They are developing a new architecture using silicon photonics and active, programmable metasurfaces to perform matrix multiplications at the speed of light, aiming for significantly higher energy efficiency and performance for AI inference. The company has a world-class team, has raised $110M in Series A funding from prominent investors, and has been recognized on the EE Times Silicon 100 list.

This position is for an experienced CAD Manager to lead and manage the EDA tooling, design flows, and physical design infrastructure for their analog and mixed-signal IC design teams. The role involves evaluating and deploying EDA tools, developing custom flows from schematic capture to tape-out, and maximizing designer productivity across multiple process nodes. The manager will collaborate with design, verification, and process engineering teams to tackle complex analog design challenges.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a closely related field.
• 8+ years of hands-on experience in analog/mixed-signal IC CAD or EDA engineering.
• Deep expertise in Cadence Virtuoso suite (schematic, layout, ADE), Spectre/Spectre X simulation, and Cadence Virtuoso SKILL scripting.
• Strong knowledge of physical verification tools: Mentor Calibre (DRC, LVS, PEX) and/or Synopsys IC Validator.
• Proven experience with PDK integration and support for advanced CMOS nodes.
• Proficiency in at least two scripting languages: Python, SKILL, Tcl, or Perl.
• Experience managing EDA tool licensing (FlexLM/RLM) and floating license optimization.
• Strong understanding of Linux/Unix computing environments and HPC cluster management.

Nice To Haves

• Hands-on experience with TSMC N3P and/or N2P process nodes strongly preferred.
• Familiarity with TSMC design rule documents (DRM), analog design guidelines (ADG), and tape-out sign-off requirements for N3P/N2P.
• Experience with custom digital/mixed-signal flows, including OpenAccess, Virtuoso Layout Suite XL, or Virtuoso RF.
• Familiarity with post-layout simulation (EMIR, noise, reliability) methodologies.
• Knowledge of EM/IR analysis tools (Voltus, RedHawk) applied to analog/custom blocks.
• Prior people management or technical lead experience in a tape-out-oriented environment.
• Experience with high-speed I/O, SerDes, PLLs, or RF circuit design CAD flows.
• Familiarity with configuration management tools and agile project tracking (SOS, JIRA, Confluence).

Responsibilities

• Evaluate, deploy, and support EDA tools, including Cadence Virtuoso, Spectre, Calibre, and related analog/custom IC toolsets.
• Develop, maintain, and optimize design flows for schematic entry, simulation, layout, parasitic extraction (PEX), and physical verification (DRC/LVS).
• Manage EDA tool licenses, vendor relationships, and tool upgrade cycles to ensure the design team’s productivity.
• Implement and maintain PDK installations and updates, coordinating with foundry partners (including TSMC) for process node enablement, with specific focus on advanced technology qualification and ramp.
• Lead CAD enablement for TSMC N3P and N2P advanced nodes, including PDK bring-up, design rule updates, fill strategy, and integration / sign-off flow alignment with TSMC requirements.
• Interface with foundries and VCA partners to facilitate a smooth tape-out process.
• Architect and maintain the CAD computing environment, including Linux workstations, EDA servers, and LSF/grid computing clusters.
• Develop and maintain SKILL, Tcl, Python, and shell scripts to automate repetitive CAD tasks and streamline designer workflows.
• Manage design data integrity through version control systems (Git, Vault, ClearCase) and define backup and archive strategies.
• Collaborate with IT to plan compute resource needs, capacity planning, and infrastructure upgrades.
• Act as the primary technical liaison between design teams, foundries, and EDA vendors.
• Define and enforce CAD best practices, design methodology guidelines, and tape-out checklists.
• Provide hands-on debug support for flow and tool issues during critical project phases and tape-out windows.
• Drive continuous improvement initiatives to reduce design cycle time and improve first-pass silicon success rates.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching.
• Stock option opportunities.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits: Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Manager