ASIC Verification Engineer

About the position

This is an onsite role with a strong preference working out of the Maynard, MA office location, but can also be based out of our San Jose, CA or RTP, NC offices. As part of a growing Design Verification Team, you will work with other verification, DSP, and RTL engineers to ensure successful verification of complex ASICs throughout its pre-silicon lifecycle. You will work with C++ and UVM building test-benches and gathering and analyzing coverage reports.

Responsibilities

• Develop detailed and comprehensive test plans.
• Develop verification test benches at block, inter-block, and chip levels.
• Apply innovative verification techniques to complex designs.
• Participate in the review of design verification coding and coverage metrics.
• Work collaboratively with the team to develop & incorporate the latest test technologies & processes.

Requirements

• Bachelor's degree and 5+ years of experience, or a Master's degree and 3+ years majoring in Computer Science, Computer Engineering, or Electronic/Electrical Engineering.
• Demonstrated experience in ASIC design verification methodologies and flows.
• Experience with C++ model co-simulation.
• Experience with HVL and HDL languages and tools, scripting and programming languages Verilog, SV, C++, Perl and/or Python.

Nice-to-haves

• UVM experience is a plus.
• Strong problem solving, communication, and team skills.
• Experience in object oriented programming.
• Networking knowledge is preferred, but not essential.

Benefits

• Quality medical, dental and vision insurance.
• 401(k) plan with a Cisco matching contribution.
• Short and long-term disability coverage.
• Basic life insurance.
• Numerous wellbeing offerings.
• Up to twelve paid holidays per calendar year.
• Flexible Vacation Time Off policy.
• Sick Time Off provided on hire date and annually.
• Paid time away to deal with critical or emergency issues.
• Additional paid time to volunteer and give back to the community.